1. Field of the Invention
The present invention relates to a semiconductor device formed in a semiconductor layer on an insulating film, particularly relates to a static random access memory formed in a semiconductor layer on an insulating film.
2. Description of the Related Art
A semiconductor memory typified by a static random access memory (hereinafter referred to as SRAM) is recently produced in the form of a large scale integrated circuit more and more. In order to realize the large scale SRAM, it is strongly desired that a cell layout can reduce a cell area and suppress difficulty of a manufacturing process.
Conventionally, various kinds of layouts of a six-transistor type of SRAM cell which is constituted by six transistors are disclosed (for example, see Jpn. Pat. Appln. KOKAI Publication No. 10-178110). FIG. 1 shows an example of a layout different from the layout disclosed in Jpn. Pat. Appln. KOKAI Publication No. 10-178110. These two layouts shown in FIG. 1 and Jpn. Pat. Appln. KOKAI Publication No. 10-178110 are characterized in that, when a pattern in the cell is rotated 180 degrees about point C, the pattern is superimposed on the original pattern and adjacent cells become the line-symmetry pattern having a line of symmetry as a cell boundary line. These layouts have a relatively larger margin in a resist forming process, so that it is expected as the future layout of the miniaturized SRAM cell.
The layout shown in FIG. 1 has a butting diffusion where an N+ type of diffusion layer is adjacent to a P+ type of diffusion layer. When the butting diffusion is used, the area of the SRAM cell can be reduced compared with the layout disclosed in Jpn. Pat. Appln. KOKAI Publication No. 10-178110. The layout shown in FIG. 1 is one which is useful in connecting the N+ type of diffusion layer to the P+ type of diffusion layer by using a thin-film SOI substrate, which has a silicon layer (thickness of about 100 nm) formed on the insulating film, and by using silicide bonded to the diffusion layer without forming a well region. The SOI (Silicon On Insulator) substrate is a substrate having the structure in which the semiconductor layer such as a silicon layer is formed on the insulating film.
In an SRAM cell 101 shown in FIG. 1, a shared contact SC commonly connected to a gate electrode GL and an active area AA is formed with a hole extending over the gate electrode GL and the active area AA. The area of the SRAM cell 101 can be reduced by using the shared contact SC. Reference symbol CVC indicates a contact supplied with power supply voltage Vcc, CVS indicates a contact supplied with reference electric potential Vss, and CBL indicates a contact connected to a bit line, respectively.
However, there are some problems in the above-described cell layout shown in FIG. 1.
First, in a narrow space between the gate electrodes with a length of about 0.1 μm, which is indicated by D1 in FIG. 1, since it is very difficult to form a mask and there is a smaller margin of a process forming a resist pattern, deviation in size of the space between the gate electrodes is increased. Accordingly, it is very difficult to produce the large scale SRAM with good reproducibility.
Secondly, in a narrow space between the gate electrodes, which is indicated by D2 in FIG. 1, there is a problem that a resist residue is easily caused by a projection indicated by P, i.e. compared with the case of absence of the projection, and the margin of the process forming the resist pattern is small.
Thirdly, in the size in a major axis direction of the shared contact SC, variation is larger than that in a minor axis direction. This is because there is the variation in the mask forming process and the resist forming process. Consequently, there is the problem that the size in a longitudinal direction (short-side direction) of the SRAM cell 101 can not be reduced because of concerns about a short circuit to the adjacent gate electrode.
In the fourth, it is necessary in the layout shown in FIG. 1 to secure a distance of an extent of resolution limit of lithography as an isolation width, indicated by D3, between p-channel MOS transistors. A width in a lateral direction, indicated by D4, between the adjacent regions is required to secure the distance, considering misalignment of the resist mask in ion implantation of an N-type impurity and a P-type impurity. Accordingly, there is the problem that the size in a lateral direction (long side direction) of the SRAM cell 101 can not be reduced.